The present invention relates to a DRAM (Dynamic Random Access Memory) integrated circuit (IC) fabrication, and more particularly to a process of fabricating DRAM capacitors by utilization of liquid phase deposition (LPD) technology.
Dynamic RAMs are well-known memory ICs in this art. Large dynamic RAMs commercially available typically employ the simplest dynamic memory cell including a single storage capacitor and one MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor). FIG. 1 illustrates a schematic circuit diagram of the dynamic memory cell. As shown in the drawing, the memory cell includes a MOS transistor 10 with its gate coupled to word line WL and drain coupled to bit line BL, and a storage capacitor 12 with a first electrode coupled to the source of the transistor 10 and a second electrode coupled to ground. The transistor 10 serves as a switch to access the capacitor 12 either to charge the capacitor 12 when information is stored in the memory cell or to determine if the capacitor 12 has been charged as information is read from the memory cell. High capacitance of the capacitor is desirable to prevent loss of stored information.
A wide variety of geometries and placements of the transistor and the capacitor have been used in the past. The majority of these geometries have used transistors and capacitors which are formed horizontally with respect to the substrate surface. This orientation of the devices usually uses a great deal of surface area and therefore increases the necessary size of a memory array. FIG. 2 illustrates a cross-sectional side view of prior art DRAM cells fabricated on a silicon substrate 2. Field oxides 20 are formed in the substrate 2 to define active regions. Patterned interconnections 22 and gates 32 typically made from highly-doped polycrystalline silicon (or called polysilicon) are formed on the field oxides 20 and the active regions, respectively. Doped source/drain regions 30 are formed in the surface of the substrate 2. Patterned insulators 24 typically made from silicon dioxide are formed to surround the interconnections 22 and gates 32. First electrode (or bottom electrode) layer 34, dielectric layer 36 and second electrode (or top electrode) layer 38 for the storage capacitors are formed over the structure. The first and second electrode layers 34 and 38 are typically made from highly-doped polysilicon, and the dielectric layer 36 typically utilizes an NO (nitride-oxide) or ONO (oxide-nitride-oxide) structure.
As shown in the drawing, the capacitors are fabricated along the rugged topography of the structure resulted from the formation of transistor devices. If higher capacitance is needed, the area of the dielectric layer 36 has to be increased. In such a prior art, the only way is to spread out the dielectric layer 36 in the horizontal direction. This will inevitably cause an increase in the necessary size per memory cell. In very high density applications, it tends to further shrink the memory cell size. This prior art will be unable to provide sufficient capacitance.